A 5564 GHz fully-integrated sub-harmonic wideband transceiver in 130 nm CMOS process

Jeng Han Tsai

doi:10.1109/LMWC.2009.2032029

A 5564 GHz fully-integrated sub-harmonic wideband transceiver in 130 nm CMOS process

Jeng Han Tsai^*

^*Corresponding author for this work

Department of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

16 Citations (Scopus)

Abstract

In this letter, a 5564 GHz compact fully-integrated gigabit transceiver with sub-harmonic pump technique is presented. The transceiver consists of a single-pole-double-throw (SPDT) traveling wave switch, a low-noise amplifier (LNA), a buffer amplifier (BA), and two sub-harmonic resistive mixers for up-conversion and down-conversion, respectively. The transceiver using 130 nm standard CMOS technology achieves an up-conversion gain of 7.4 dB at 62 GHz and down-conversion gain of 7.2 dB at 60 GHz with a compact chip size of 1.2 mm ²The 3 dB frequency bandwidth ranges from 55 to 64 GHz, which can cover the whole frequency band for 802.15.TG3C WPAN applications. For system applications, gigabit BPSK modulation signal test is successfully performed in this work.

Original language	English
Article number	5290006
Pages (from-to)	758-760
Number of pages	3
Journal	IEEE Microwave and Wireless Components Letters
Volume	19
Issue number	11
DOIs	https://doi.org/10.1109/LMWC.2009.2032029
Publication status	Published - 2009 Nov

Keywords

60 GHz
CMOS
Gigabit
Millimeter-wave (MMW)
Sub-harmonic
Transceiver

ASJC Scopus subject areas

Condensed Matter Physics
Electrical and Electronic Engineering

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10.1109/LMWC.2009.2032029

Cite this

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title = "A 5564 GHz fully-integrated sub-harmonic wideband transceiver in 130 nm CMOS process",

abstract = "In this letter, a 5564 GHz compact fully-integrated gigabit transceiver with sub-harmonic pump technique is presented. The transceiver consists of a single-pole-double-throw (SPDT) traveling wave switch, a low-noise amplifier (LNA), a buffer amplifier (BA), and two sub-harmonic resistive mixers for up-conversion and down-conversion, respectively. The transceiver using 130 nm standard CMOS technology achieves an up-conversion gain of 7.4 dB at 62 GHz and down-conversion gain of 7.2 dB at 60 GHz with a compact chip size of 1.2 mm 2The 3 dB frequency bandwidth ranges from 55 to 64 GHz, which can cover the whole frequency band for 802.15.TG3C WPAN applications. For system applications, gigabit BPSK modulation signal test is successfully performed in this work.",

keywords = "60 GHz, CMOS, Gigabit, Millimeter-wave (MMW), Sub-harmonic, Transceiver",

author = "Tsai, {Jeng Han}",

note = "Funding Information: Manuscript received June 06, 2009; revised August 05, 2009. First published October 20, 2009; current version published November 06, 2009. This work was supported by the National Science Council of Taiwan under Grants 97-2218-E-155-009 and 98-2221-E-155-009-MY2, by the Graduate Institute of Communication Engineering, National Taiwan University, and by the National Chip Implementation Center (CIC), Taiwan.",

year = "2009",

month = nov,

doi = "10.1109/LMWC.2009.2032029",

language = "English",

volume = "19",

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AU - Tsai, Jeng Han

N1 - Funding Information: Manuscript received June 06, 2009; revised August 05, 2009. First published October 20, 2009; current version published November 06, 2009. This work was supported by the National Science Council of Taiwan under Grants 97-2218-E-155-009 and 98-2221-E-155-009-MY2, by the Graduate Institute of Communication Engineering, National Taiwan University, and by the National Chip Implementation Center (CIC), Taiwan.

PY - 2009/11

Y1 - 2009/11

N2 - In this letter, a 5564 GHz compact fully-integrated gigabit transceiver with sub-harmonic pump technique is presented. The transceiver consists of a single-pole-double-throw (SPDT) traveling wave switch, a low-noise amplifier (LNA), a buffer amplifier (BA), and two sub-harmonic resistive mixers for up-conversion and down-conversion, respectively. The transceiver using 130 nm standard CMOS technology achieves an up-conversion gain of 7.4 dB at 62 GHz and down-conversion gain of 7.2 dB at 60 GHz with a compact chip size of 1.2 mm 2The 3 dB frequency bandwidth ranges from 55 to 64 GHz, which can cover the whole frequency band for 802.15.TG3C WPAN applications. For system applications, gigabit BPSK modulation signal test is successfully performed in this work.

AB - In this letter, a 5564 GHz compact fully-integrated gigabit transceiver with sub-harmonic pump technique is presented. The transceiver consists of a single-pole-double-throw (SPDT) traveling wave switch, a low-noise amplifier (LNA), a buffer amplifier (BA), and two sub-harmonic resistive mixers for up-conversion and down-conversion, respectively. The transceiver using 130 nm standard CMOS technology achieves an up-conversion gain of 7.4 dB at 62 GHz and down-conversion gain of 7.2 dB at 60 GHz with a compact chip size of 1.2 mm 2The 3 dB frequency bandwidth ranges from 55 to 64 GHz, which can cover the whole frequency band for 802.15.TG3C WPAN applications. For system applications, gigabit BPSK modulation signal test is successfully performed in this work.

KW - 60 GHz

KW - CMOS

KW - Gigabit

KW - Millimeter-wave (MMW)

KW - Sub-harmonic

KW - Transceiver

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A 5564 GHz fully-integrated sub-harmonic wideband transceiver in 130 nm CMOS process

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Keywords

ASJC Scopus subject areas

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