A 5.5 GHz low-power PLL using 0.18-μm CMOS technology

Jeng Han Tsai; Shao Wei Huang; Jian Ping Chou

doi:10.1109/RWS.2014.6830071

A 5.5 GHz low-power PLL using 0.18-μm CMOS technology

Jeng Han Tsai, Shao Wei Huang, Jian Ping Chou

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

9 Citations (Scopus)

Abstract

This paper presents a fully-integrated 5.5 GHz low-power consumption phase-locked loop (PLL) on standard 0.18-μm CMOS process. Utilizing the transformer feedback VCO and high speed true single phase clock (TSPC) divider, the 5.5 GHz PLL achieves low power consumption of 9.23 mW. In addition, a rail-to-rail buffer amplifier is incorporated between the VCO and TSPC divider chain to provide full voltage swing for TSPC input. The measured phase noises are -85 dBc/Hz and -116.6 dBc/Hz at 1 MHz and 10 MHz frequency offsets, respectively.

Original language	English
Title of host publication	RWS 2014 - Proceedings
Subtitle of host publication	2014 IEEE Radio and Wireless Symposium
Publisher	IEEE Computer Society
Pages	205-207
Number of pages	3
ISBN (Print)	9781479921812
DOIs	https://doi.org/10.1109/RWS.2014.6830071
Publication status	Published - 2014
Event	2014 IEEE Radio and Wireless Symposium, RWS 2014 - Newport Beach, CA, United States Duration: 2014 Jan 19 → 2014 Jan 22

Publication series

Name	IEEE Radio and Wireless Symposium, RWS
ISSN (Print)	2164-2958
ISSN (Electronic)	2164-2974

Other

Other	2014 IEEE Radio and Wireless Symposium, RWS 2014
Country/Territory	United States
City	Newport Beach, CA
Period	2014/01/19 → 2014/01/22

Keywords

CMOS
Phase-locked loop (PLL)
lower power
radio frequency integration circuit (RFIC)

ASJC Scopus subject areas

Computer Networks and Communications
Computer Science Applications
Electrical and Electronic Engineering
Communication

Access to Document

10.1109/RWS.2014.6830071

Cite this

Tsai, JH, Huang, SW & Chou, JP 2014, A 5.5 GHz low-power PLL using 0.18-μm CMOS technology. in RWS 2014 - Proceedings: 2014 IEEE Radio and Wireless Symposium., 6830071, IEEE Radio and Wireless Symposium, RWS, IEEE Computer Society, pp. 205-207, 2014 IEEE Radio and Wireless Symposium, RWS 2014, Newport Beach, CA, United States, 2014/01/19. https://doi.org/10.1109/RWS.2014.6830071

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title = "A 5.5 GHz low-power PLL using 0.18-μm CMOS technology",

abstract = "This paper presents a fully-integrated 5.5 GHz low-power consumption phase-locked loop (PLL) on standard 0.18-μm CMOS process. Utilizing the transformer feedback VCO and high speed true single phase clock (TSPC) divider, the 5.5 GHz PLL achieves low power consumption of 9.23 mW. In addition, a rail-to-rail buffer amplifier is incorporated between the VCO and TSPC divider chain to provide full voltage swing for TSPC input. The measured phase noises are -85 dBc/Hz and -116.6 dBc/Hz at 1 MHz and 10 MHz frequency offsets, respectively.",

keywords = "CMOS, Phase-locked loop (PLL), lower power, radio frequency integration circuit (RFIC)",

author = "Tsai, {Jeng Han} and Huang, {Shao Wei} and Chou, {Jian Ping}",

year = "2014",

doi = "10.1109/RWS.2014.6830071",

language = "English",

isbn = "9781479921812",

series = "IEEE Radio and Wireless Symposium, RWS",

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booktitle = "RWS 2014 - Proceedings",

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AU - Tsai, Jeng Han

AU - Huang, Shao Wei

AU - Chou, Jian Ping

PY - 2014

Y1 - 2014

N2 - This paper presents a fully-integrated 5.5 GHz low-power consumption phase-locked loop (PLL) on standard 0.18-μm CMOS process. Utilizing the transformer feedback VCO and high speed true single phase clock (TSPC) divider, the 5.5 GHz PLL achieves low power consumption of 9.23 mW. In addition, a rail-to-rail buffer amplifier is incorporated between the VCO and TSPC divider chain to provide full voltage swing for TSPC input. The measured phase noises are -85 dBc/Hz and -116.6 dBc/Hz at 1 MHz and 10 MHz frequency offsets, respectively.

AB - This paper presents a fully-integrated 5.5 GHz low-power consumption phase-locked loop (PLL) on standard 0.18-μm CMOS process. Utilizing the transformer feedback VCO and high speed true single phase clock (TSPC) divider, the 5.5 GHz PLL achieves low power consumption of 9.23 mW. In addition, a rail-to-rail buffer amplifier is incorporated between the VCO and TSPC divider chain to provide full voltage swing for TSPC input. The measured phase noises are -85 dBc/Hz and -116.6 dBc/Hz at 1 MHz and 10 MHz frequency offsets, respectively.

KW - CMOS

KW - Phase-locked loop (PLL)

KW - lower power

KW - radio frequency integration circuit (RFIC)

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BT - RWS 2014 - Proceedings

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ER -

A 5.5 GHz low-power PLL using 0.18-μm CMOS technology

Abstract

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Keywords

ASJC Scopus subject areas

Access to Document

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