A 5.5 GHz low-power PLL using 0.18-μm CMOS technology

Jeng Han Tsai, Shao Wei Huang, Jian Ping Chou

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)


This paper presents a fully-integrated 5.5 GHz low-power consumption phase-locked loop (PLL) on standard 0.18-μm CMOS process. Utilizing the transformer feedback VCO and high speed true single phase clock (TSPC) divider, the 5.5 GHz PLL achieves low power consumption of 9.23 mW. In addition, a rail-to-rail buffer amplifier is incorporated between the VCO and TSPC divider chain to provide full voltage swing for TSPC input. The measured phase noises are -85 dBc/Hz and -116.6 dBc/Hz at 1 MHz and 10 MHz frequency offsets, respectively.

Original languageEnglish
Title of host publicationRWS 2014 - Proceedings
Subtitle of host publication2014 IEEE Radio and Wireless Symposium
PublisherIEEE Computer Society
Number of pages3
ISBN (Print)9781479921812
Publication statusPublished - 2014
Event2014 IEEE Radio and Wireless Symposium, RWS 2014 - Newport Beach, CA, United States
Duration: 2014 Jan 192014 Jan 22

Publication series

NameIEEE Radio and Wireless Symposium, RWS
ISSN (Print)2164-2958
ISSN (Electronic)2164-2974


Other2014 IEEE Radio and Wireless Symposium, RWS 2014
Country/TerritoryUnited States
CityNewport Beach, CA


  • CMOS
  • Phase-locked loop (PLL)
  • lower power
  • radio frequency integration circuit (RFIC)

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Computer Science Applications
  • Electrical and Electronic Engineering
  • Communication


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