A 5.5 GHz low-power PLL using 0.18-μm CMOS technology

Jeng Han Tsai, Shao Wei Huang, Jian Ping Chou

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

This paper presents a fully-integrated 5.5 GHz low-power consumption phase-locked loop (PLL) on standard 0.18-μm CMOS process. Utilizing the transformer feedback VCO and high speed true single phase clock (TSPC) divider, the 5.5 GHz PLL achieves low power consumption of 9.23 mW. In addition, a rail-to-rail buffer amplifier is incorporated between the VCO and TSPC divider chain to provide full voltage swing for TSPC input. The measured phase noises are -85 dBc/Hz and -116.6 dBc/Hz at 1 MHz and 10 MHz frequency offsets, respectively.

Original languageEnglish
Title of host publicationRWS 2014 - Proceedings
Subtitle of host publication2014 IEEE Radio and Wireless Symposium
PublisherIEEE Computer Society
Pages205-207
Number of pages3
ISBN (Print)9781479921812
DOIs
Publication statusPublished - 2014 Jan 1
Event2014 IEEE Radio and Wireless Symposium, RWS 2014 - Newport Beach, CA, United States
Duration: 2014 Jan 192014 Jan 22

Other

Other2014 IEEE Radio and Wireless Symposium, RWS 2014
CountryUnited States
CityNewport Beach, CA
Period14/1/1914/1/22

Fingerprint

Phase locked loops
Clocks
Variable frequency oscillators
Rails
Electric power utilization
Buffer amplifiers
Phase noise
Feedback
Electric potential

Keywords

  • CMOS
  • lower power
  • Phase-locked loop (PLL)
  • radio frequency integration circuit (RFIC)

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Computer Science Applications
  • Electrical and Electronic Engineering
  • Communication

Cite this

Tsai, J. H., Huang, S. W., & Chou, J. P. (2014). A 5.5 GHz low-power PLL using 0.18-μm CMOS technology. In RWS 2014 - Proceedings: 2014 IEEE Radio and Wireless Symposium (pp. 205-207). [6830071] IEEE Computer Society. https://doi.org/10.1109/RWS.2014.6830071

A 5.5 GHz low-power PLL using 0.18-μm CMOS technology. / Tsai, Jeng Han; Huang, Shao Wei; Chou, Jian Ping.

RWS 2014 - Proceedings: 2014 IEEE Radio and Wireless Symposium. IEEE Computer Society, 2014. p. 205-207 6830071.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Tsai, JH, Huang, SW & Chou, JP 2014, A 5.5 GHz low-power PLL using 0.18-μm CMOS technology. in RWS 2014 - Proceedings: 2014 IEEE Radio and Wireless Symposium., 6830071, IEEE Computer Society, pp. 205-207, 2014 IEEE Radio and Wireless Symposium, RWS 2014, Newport Beach, CA, United States, 14/1/19. https://doi.org/10.1109/RWS.2014.6830071
Tsai JH, Huang SW, Chou JP. A 5.5 GHz low-power PLL using 0.18-μm CMOS technology. In RWS 2014 - Proceedings: 2014 IEEE Radio and Wireless Symposium. IEEE Computer Society. 2014. p. 205-207. 6830071 https://doi.org/10.1109/RWS.2014.6830071
Tsai, Jeng Han ; Huang, Shao Wei ; Chou, Jian Ping. / A 5.5 GHz low-power PLL using 0.18-μm CMOS technology. RWS 2014 - Proceedings: 2014 IEEE Radio and Wireless Symposium. IEEE Computer Society, 2014. pp. 205-207
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