A 5.2 GHz haft-watt fully-integrated CMOS power amplifier

Jeng Han Tsai; Chen Fang Lin; Po Chun Shen; Hong Wun Ou-Yang

doi:10.1109/GCCE46687.2019.9015402

A 5.2 GHz haft-watt fully-integrated CMOS power amplifier

Jeng Han Tsai^*, Chen Fang Lin, Po Chun Shen, Hong Wun Ou-Yang

^*Corresponding author for this work

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

A 5.2 GHz fully-integrated power amplifier is designed and fabricated using 0.18-μm 1P6M bulk CMOS technology. Utilizing a 2-way series combining transformer, the CMOS PA achieves a measured maximum saturation output power (Psat) of 27.6 dBm at 5.2 GHz within a compact chip size of 1.2 mm × 1 mm. The measured small signal gain is 13.4 dB, the output 1-dB compression point (OP1dB) is 23.5 dBm, and the peak power-added efficiency (PAE) is 19.2 % at 5.2 GHz. For IEEE 802.11ac WLAN 64-QAM OFDM modulation signal test, the PA meets the EVM requirement of 5.6% (-25 dB) at the linear output power of 16.6 dBm.

Original language	English
Title of host publication	2019 IEEE 8th Global Conference on Consumer Electronics, GCCE 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	407-408
Number of pages	2
ISBN (Electronic)	9781728135755
DOIs	https://doi.org/10.1109/GCCE46687.2019.9015402
Publication status	Published - 2019 Oct
Event	8th IEEE Global Conference on Consumer Electronics, GCCE 2019 - Osaka, Japan Duration: 2019 Oct 15 → 2019 Oct 18

Publication series

Name	2019 IEEE 8th Global Conference on Consumer Electronics, GCCE 2019

Conference

Conference	8th IEEE Global Conference on Consumer Electronics, GCCE 2019
Country/Territory	Japan
City	Osaka
Period	2019/10/15 → 2019/10/18

Keywords

CMOS
Power amplifier (PA)
Radio frequency integrated circuit (RFIC)
Transformer

ASJC Scopus subject areas

Instrumentation
Artificial Intelligence
Computer Networks and Communications
Computer Science Applications
Electrical and Electronic Engineering

Access to Document

10.1109/GCCE46687.2019.9015402

Cite this

Tsai, J. H., Lin, C. F., Shen, P. C., & Ou-Yang, H. W. (2019). A 5.2 GHz haft-watt fully-integrated CMOS power amplifier. In 2019 IEEE 8th Global Conference on Consumer Electronics, GCCE 2019 (pp. 407-408). Article 9015402 (2019 IEEE 8th Global Conference on Consumer Electronics, GCCE 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/GCCE46687.2019.9015402

A 5.2 GHz haft-watt fully-integrated CMOS power amplifier. / Tsai, Jeng Han; Lin, Chen Fang; Shen, Po Chun et al.
2019 IEEE 8th Global Conference on Consumer Electronics, GCCE 2019. Institute of Electrical and Electronics Engineers Inc., 2019. p. 407-408 9015402 (2019 IEEE 8th Global Conference on Consumer Electronics, GCCE 2019).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Tsai, JH, Lin, CF, Shen, PC & Ou-Yang, HW 2019, A 5.2 GHz haft-watt fully-integrated CMOS power amplifier. in 2019 IEEE 8th Global Conference on Consumer Electronics, GCCE 2019., 9015402, 2019 IEEE 8th Global Conference on Consumer Electronics, GCCE 2019, Institute of Electrical and Electronics Engineers Inc., pp. 407-408, 8th IEEE Global Conference on Consumer Electronics, GCCE 2019, Osaka, Japan, 2019/10/15. https://doi.org/10.1109/GCCE46687.2019.9015402

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title = "A 5.2 GHz haft-watt fully-integrated CMOS power amplifier",

abstract = "A 5.2 GHz fully-integrated power amplifier is designed and fabricated using 0.18-μm 1P6M bulk CMOS technology. Utilizing a 2-way series combining transformer, the CMOS PA achieves a measured maximum saturation output power (Psat) of 27.6 dBm at 5.2 GHz within a compact chip size of 1.2 mm × 1 mm. The measured small signal gain is 13.4 dB, the output 1-dB compression point (OP1dB) is 23.5 dBm, and the peak power-added efficiency (PAE) is 19.2 % at 5.2 GHz. For IEEE 802.11ac WLAN 64-QAM OFDM modulation signal test, the PA meets the EVM requirement of 5.6% (-25 dB) at the linear output power of 16.6 dBm.",

keywords = "CMOS, Power amplifier (PA), Radio frequency integrated circuit (RFIC), Transformer",

author = "Tsai, {Jeng Han} and Lin, {Chen Fang} and Shen, {Po Chun} and Ou-Yang, {Hong Wun}",

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AB - A 5.2 GHz fully-integrated power amplifier is designed and fabricated using 0.18-μm 1P6M bulk CMOS technology. Utilizing a 2-way series combining transformer, the CMOS PA achieves a measured maximum saturation output power (Psat) of 27.6 dBm at 5.2 GHz within a compact chip size of 1.2 mm × 1 mm. The measured small signal gain is 13.4 dB, the output 1-dB compression point (OP1dB) is 23.5 dBm, and the peak power-added efficiency (PAE) is 19.2 % at 5.2 GHz. For IEEE 802.11ac WLAN 64-QAM OFDM modulation signal test, the PA meets the EVM requirement of 5.6% (-25 dB) at the linear output power of 16.6 dBm.

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KW - Radio frequency integrated circuit (RFIC)

KW - Transformer

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A 5.2 GHz haft-watt fully-integrated CMOS power amplifier

Abstract

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Keywords

ASJC Scopus subject areas

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