A 5 GHz fully-integrated low-power phase-locked loop using 0.18-μm CMOS technology

Jeng Han Tsai, Chuan Jung Huang, Tse Yi Hsieh, Shao Wei Huang

Research output: Contribution to journalArticle

Abstract

A 5 GHz fully integrated low-power phase-locked loop (PLL) was designed and fabricated on 0.18-μm CMOS process. To achieve low power consumption, the transformer feedback VCO and high speed true single phase clock (TSPC) divider were adopted. A rail-to-rail buffer amplifier was incorporated between the VCO and TSPC divider chain to provide full voltage swing for TSPC input. In addition, dual varactor pairs were utilized to enlarge the tuning rage of the VCO while maintaining the low KVCO. The PLL achieved low power of 12.12 mW with good phase noise. The closed loop phase noises were -90.88 and -115.8 dBc/Hz at 100 kHz and 10 MHz frequency offsets.

Original languageEnglish
Pages (from-to)1534-1537
Number of pages4
JournalMicrowave and Optical Technology Letters
Volume58
Issue number7
DOIs
Publication statusPublished - 2016 Jul 1

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Keywords

  • CMOS
  • phase-locked loop (PLL)
  • radio frequency integration circuit (RFIC)

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Atomic and Molecular Physics, and Optics
  • Condensed Matter Physics
  • Electrical and Electronic Engineering

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