A 40.96-GOPS 196.8-mW Digital Logic Accelerator Used in DNN for Underwater Object Recognition

Chua Chin Wang; Ralph Gerard B. Sangalang; Chien Ping Kuo; Hsin Che Wu; Yi Hsu; Shen Fu Hsiao; Chia Hung Yeh

doi:10.1109/TCSI.2022.3187450

A 40.96-GOPS 196.8-mW Digital Logic Accelerator Used in DNN for Underwater Object Recognition

Chua Chin Wang^*, Ralph Gerard B. Sangalang, Chien Ping Kuo, Hsin Che Wu, Yi Hsu, Shen Fu Hsiao, Chia Hung Yeh

^*Corresponding author for this work

Department of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

2 Citations (Scopus)

Abstract

This investigation presents a digital logic accelerator (DLA) design of a neural network hardware that utilizes output reuse. The DLA is used in the detection mechanism of underwater objects that was deployed in an underwater vehicle. A modified YoloV3-tiny network was also implemented to detect more than 20 underwater objects. The proposed DLA uses processing units that have parallel architectures of output windows, and output channels. Moreover, a new Inter-Controller is designed to control the direct memory access (DMA) together with a new Reshape module to improve the performance and power efficiency. A detailed description of the design as well as the measurements on silicon are presented. The chip is realized using a typical 180-nm CMOS process. It showed a performance result of 40.96 GOPS and the power consumption is 196.8 mW. The DLA was tested to demonstrate 19.88 frames per second and 40.96 GOPS.

Original language	English
Pages (from-to)	4860-4871
Number of pages	12
Journal	IEEE Transactions on Circuits and Systems I: Regular Papers
Volume	69
Issue number	12
DOIs	https://doi.org/10.1109/TCSI.2022.3187450
Publication status	Published - 2022 Dec 1

Keywords

Deep learning
deep neural networks (DNN)
energy efficient
hardware accelerators
reshape module

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/TCSI.2022.3187450

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title = "A 40.96-GOPS 196.8-mW Digital Logic Accelerator Used in DNN for Underwater Object Recognition",

abstract = "This investigation presents a digital logic accelerator (DLA) design of a neural network hardware that utilizes output reuse. The DLA is used in the detection mechanism of underwater objects that was deployed in an underwater vehicle. A modified YoloV3-tiny network was also implemented to detect more than 20 underwater objects. The proposed DLA uses processing units that have parallel architectures of output windows, and output channels. Moreover, a new Inter-Controller is designed to control the direct memory access (DMA) together with a new Reshape module to improve the performance and power efficiency. A detailed description of the design as well as the measurements on silicon are presented. The chip is realized using a typical 180-nm CMOS process. It showed a performance result of 40.96 GOPS and the power consumption is 196.8 mW. The DLA was tested to demonstrate 19.88 frames per second and 40.96 GOPS.",

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author = "Wang, {Chua Chin} and Sangalang, {Ralph Gerard B.} and Kuo, {Chien Ping} and Wu, {Hsin Che} and Yi Hsu and Hsiao, {Shen Fu} and Yeh, {Chia Hung}",

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AU - Kuo, Chien Ping

AU - Wu, Hsin Che

AU - Hsu, Yi

AU - Hsiao, Shen Fu

AU - Yeh, Chia Hung

PY - 2022/12/1

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N2 - This investigation presents a digital logic accelerator (DLA) design of a neural network hardware that utilizes output reuse. The DLA is used in the detection mechanism of underwater objects that was deployed in an underwater vehicle. A modified YoloV3-tiny network was also implemented to detect more than 20 underwater objects. The proposed DLA uses processing units that have parallel architectures of output windows, and output channels. Moreover, a new Inter-Controller is designed to control the direct memory access (DMA) together with a new Reshape module to improve the performance and power efficiency. A detailed description of the design as well as the measurements on silicon are presented. The chip is realized using a typical 180-nm CMOS process. It showed a performance result of 40.96 GOPS and the power consumption is 196.8 mW. The DLA was tested to demonstrate 19.88 frames per second and 40.96 GOPS.

AB - This investigation presents a digital logic accelerator (DLA) design of a neural network hardware that utilizes output reuse. The DLA is used in the detection mechanism of underwater objects that was deployed in an underwater vehicle. A modified YoloV3-tiny network was also implemented to detect more than 20 underwater objects. The proposed DLA uses processing units that have parallel architectures of output windows, and output channels. Moreover, a new Inter-Controller is designed to control the direct memory access (DMA) together with a new Reshape module to improve the performance and power efficiency. A detailed description of the design as well as the measurements on silicon are presented. The chip is realized using a typical 180-nm CMOS process. It showed a performance result of 40.96 GOPS and the power consumption is 196.8 mW. The DLA was tested to demonstrate 19.88 frames per second and 40.96 GOPS.

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KW - energy efficient

KW - hardware accelerators

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A 40.96-GOPS 196.8-mW Digital Logic Accelerator Used in DNN for Underwater Object Recognition

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Keywords

ASJC Scopus subject areas

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