A 40-nm CMOS Multifunctional Computing-in-Memory (CIM) Using Single-Ended Disturb-Free 7T 1-Kb SRAM

Chua Chin Wang*, Lean Karlo S. Tolentino, Chia Yi Huang, Chia Hung Yeh

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

2 Citations (Scopus)

Abstract

This investigation proposes a computing-in-memory (CIM) design to circumvent the von Neumann bottleneck which causes limited computation throughput for effective artificial intelligence (AI) applications. The proposed CIM performs multiple operations such as single-instruction basic Boolean operations, addition, and signed number multiplication, and multiple functions such as normal mode and retention mode for the built-in self-test (BIST). Its 2T-Switch requires only two transistors to be utilized for static random-access memory (SRAM) array; thus, the arithmetic unit can be chosen easily and the area overhead is minimized. Its ripple carry adder and multiplier (RCAM) unit based on single-ended disturb-free 7T 1-Kb SRAM was developed using the full swing-gate diffusion input (FS-GDI) technology that has full voltage swing resolution, low power consumption, and less chip area cost. Its Auto-Switching Write Back Circuit restores addition and multiplication operations automatically to assigned memory address. The CIM is implemented using the TSMC 40-nm CMOS process, where the core area is $432.81 \times 510.265\,\,\mu \text{m}^{2}$. Among the related works, the proposed CIM performs the most number of operations and functions.

Original languageEnglish
Pages (from-to)2172-2185
Number of pages14
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume29
Issue number12
DOIs
Publication statusPublished - 2021 Dec 1

Keywords

  • Computing-in-memory (CIM)
  • disturb-free
  • full swing-gate diffusion input (FS-GDI)
  • static random-access memory (SRAM)
  • von Neumann bottleneck

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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