A 24-GHz 65-nm CMOS 3-D Radial and Vertically Stacked Transmitter Front-End IC for Vital-sign Detection Radar Applications

Yi Hsien Lin, Ti Yu Chao, Shao Cheng Hsiao, Yen Ju Huang, You Jen Liang, Jeng Han Tsai, Hamed Alsuraisry, Tian Wei Huang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In contrast to the conventional horizontal routings in chip layout, a 24-GHz three dimensional transmitter front-end integrated circuit architecture with vertical signal paths implemented by a 1P9M 65-nm CMOS technology is proposed in this article. With the up-converison ring mixer located at the center of the layout with its traces routed on the bottom, and four power amplifier cells radially distributed on the four quadrants of the chip with their traces at the top metals, an ultra-small core area of 0.27 mm2 is occupied. Besides, layout symmetry is ensured and heat dissipation problem might be alleviated. The transmitter has a 3-dB bandwidth from 21 to 28 GHz. The measured conversion gain and saturation power (Psat) are 3 dB and 5.5 dBm, respectively, under 14 mW DC-power consumption (PDC) at 24 GHz.

Original languageEnglish
Title of host publication2022 Asia-Pacific Microwave Conference, APMC 2022 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages282-284
Number of pages3
ISBN (Electronic)9784902339567
DOIs
Publication statusPublished - 2022
Event2022 Asia-Pacific Microwave Conference, APMC 2022 - Yokohama, Japan
Duration: 2022 Nov 292022 Dec 2

Publication series

NameAsia-Pacific Microwave Conference Proceedings, APMC
Volume2022-November
ISSN (Electronic)2690-3946

Conference

Conference2022 Asia-Pacific Microwave Conference, APMC 2022
Country/TerritoryJapan
CityYokohama
Period2022/11/292022/12/02

Keywords

  • 65-nm CMOS
  • power amplifier
  • ring mixer
  • three-dimensional integrated circuit (3-D IC)
  • transmitter front-end

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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