A 24-GHz 3.8-dB NF low-noise amplifier with built-in linearizer

Yen Hung Kuo, Jeng Han Tsai, Wei Hung Chou, Tian Wei Huang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

A K-band low-noise amplifier with built-in linearizer using 0.18-μm CMOS technology is presented in this paper. To achieve good linearity at high frequency, a distributed derivative superposition linearization technique is used. The measured results show that the improvement of IIP3 and IM3 are 5.3 dB and 10.6 dB at 24 GHz, respectively. The proposed LNA has a noise figure of 3.8 dB and a peak gain of 13.7 dB while consuming 18 mW dc power. To the best of our knowledge, this is the first LNA with a built-in linearizer above 20 GHz in CMOS.

Original languageEnglish
Title of host publication2010 Asia-Pacific Microwave Conference Proceedings, APMC 2010
Pages1505-1508
Number of pages4
Publication statusPublished - 2010 Dec 1
Event2010 Asia-Pacific Microwave Conference, APMC 2010 - Yokohama, Japan
Duration: 2010 Dec 72010 Dec 10

Publication series

NameAsia-Pacific Microwave Conference Proceedings, APMC

Other

Other2010 Asia-Pacific Microwave Conference, APMC 2010
CountryJapan
CityYokohama
Period10/12/710/12/10

Keywords

  • CMOS
  • K-band
  • linearizer
  • low noise amplifier (LNA)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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    Kuo, Y. H., Tsai, J. H., Chou, W. H., & Huang, T. W. (2010). A 24-GHz 3.8-dB NF low-noise amplifier with built-in linearizer. In 2010 Asia-Pacific Microwave Conference Proceedings, APMC 2010 (pp. 1505-1508). [5728169] (Asia-Pacific Microwave Conference Proceedings, APMC).