A 224–448 MHz low-power fully integrated phase-locked loop using 0.18-μm CMOS process

Jeng-Han Tsai, Chia Lung Lin, Yin Ting Kuo

Research output: Contribution to journalArticle

Abstract

A 224-448 MHz low-power fully integrated phase-locked loop (PLL) is designed and implemented in standard 0.18-μm CMOS process. For wide tuning rage and compact circuit size, a differential ring-type voltage-controlled oscillator (VCO) is adopted. The replica bias circuit is added to provide the required voltage for the delay cell of the VCO. For low dc consumption, a high-speed true single phase clock (TSPC) divider is used. The PLL achieves wide operating frequency from 224 to 448 MHz with low dc power consumption of 2.62 mW from 1.8 V voltage supply. The measured phase noises are −98 and −115 dBc/Hz at 100 kHz and 10 MHz frequency offsets, respectively.

Original languageEnglish
Pages (from-to)1750-1755
Number of pages6
JournalMicrowave and Optical Technology Letters
Volume59
Issue number7
DOIs
Publication statusPublished - 2017 Jul 1

Fingerprint

voltage controlled oscillators
Variable frequency oscillators
Phase locked loops
CMOS
Networks (circuits)
dividers
Electric potential
electric potential
Phase noise
replicas
clocks
Clocks
Electric power utilization
Tuning
tuning
high speed
rings
cells

Keywords

  • CMOS
  • phase-locked loop (PLL)
  • radio frequency integration circuit (RFIC)
  • ring oscillator

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Atomic and Molecular Physics, and Optics
  • Condensed Matter Physics
  • Electrical and Electronic Engineering

Cite this

A 224–448 MHz low-power fully integrated phase-locked loop using 0.18-μm CMOS process. / Tsai, Jeng-Han; Lin, Chia Lung; Kuo, Yin Ting.

In: Microwave and Optical Technology Letters, Vol. 59, No. 7, 01.07.2017, p. 1750-1755.

Research output: Contribution to journalArticle

@article{1424bb88143b4fcbab9c7d44b6cc97f6,
title = "A 224–448 MHz low-power fully integrated phase-locked loop using 0.18-μm CMOS process",
abstract = "A 224-448 MHz low-power fully integrated phase-locked loop (PLL) is designed and implemented in standard 0.18-μm CMOS process. For wide tuning rage and compact circuit size, a differential ring-type voltage-controlled oscillator (VCO) is adopted. The replica bias circuit is added to provide the required voltage for the delay cell of the VCO. For low dc consumption, a high-speed true single phase clock (TSPC) divider is used. The PLL achieves wide operating frequency from 224 to 448 MHz with low dc power consumption of 2.62 mW from 1.8 V voltage supply. The measured phase noises are −98 and −115 dBc/Hz at 100 kHz and 10 MHz frequency offsets, respectively.",
keywords = "CMOS, phase-locked loop (PLL), radio frequency integration circuit (RFIC), ring oscillator",
author = "Jeng-Han Tsai and Lin, {Chia Lung} and Kuo, {Yin Ting}",
year = "2017",
month = "7",
day = "1",
doi = "10.1002/mop.30620",
language = "English",
volume = "59",
pages = "1750--1755",
journal = "Microwave and Optical Technology Letters",
issn = "0895-2477",
publisher = "John Wiley and Sons Inc.",
number = "7",

}

TY - JOUR

T1 - A 224–448 MHz low-power fully integrated phase-locked loop using 0.18-μm CMOS process

AU - Tsai, Jeng-Han

AU - Lin, Chia Lung

AU - Kuo, Yin Ting

PY - 2017/7/1

Y1 - 2017/7/1

N2 - A 224-448 MHz low-power fully integrated phase-locked loop (PLL) is designed and implemented in standard 0.18-μm CMOS process. For wide tuning rage and compact circuit size, a differential ring-type voltage-controlled oscillator (VCO) is adopted. The replica bias circuit is added to provide the required voltage for the delay cell of the VCO. For low dc consumption, a high-speed true single phase clock (TSPC) divider is used. The PLL achieves wide operating frequency from 224 to 448 MHz with low dc power consumption of 2.62 mW from 1.8 V voltage supply. The measured phase noises are −98 and −115 dBc/Hz at 100 kHz and 10 MHz frequency offsets, respectively.

AB - A 224-448 MHz low-power fully integrated phase-locked loop (PLL) is designed and implemented in standard 0.18-μm CMOS process. For wide tuning rage and compact circuit size, a differential ring-type voltage-controlled oscillator (VCO) is adopted. The replica bias circuit is added to provide the required voltage for the delay cell of the VCO. For low dc consumption, a high-speed true single phase clock (TSPC) divider is used. The PLL achieves wide operating frequency from 224 to 448 MHz with low dc power consumption of 2.62 mW from 1.8 V voltage supply. The measured phase noises are −98 and −115 dBc/Hz at 100 kHz and 10 MHz frequency offsets, respectively.

KW - CMOS

KW - phase-locked loop (PLL)

KW - radio frequency integration circuit (RFIC)

KW - ring oscillator

UR - http://www.scopus.com/inward/record.url?scp=85019456252&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85019456252&partnerID=8YFLogxK

U2 - 10.1002/mop.30620

DO - 10.1002/mop.30620

M3 - Article

AN - SCOPUS:85019456252

VL - 59

SP - 1750

EP - 1755

JO - Microwave and Optical Technology Letters

JF - Microwave and Optical Technology Letters

SN - 0895-2477

IS - 7

ER -