A 20 to 24 GHz + 16.8 dBm fully integrated power amplifier using 0.18 μm CMOS process

Yung Nien Jen, Jeng Han Tsai, Chung Te Peng, Tian Wei Huang

Research output: Contribution to journalArticle

39 Citations (Scopus)


A 2024 GHz, fully integrated power amplifier (PA) with on-chip input and output matching is realized in 0.18 μm standard CMOS process. By cascading two cascode stages, the PA achieves 15 dB small signal gain, 10.7% power added efficiency, 16.8 dBm output saturation power and high power density per chip area of 0.137 W/mm2, which is believed to be the highest power density to our knowledge. The whole chip area with pads is 0.35 W/mm 2, which is the smallest one compared to all reported paper.

Original languageEnglish
Article number4729652
Pages (from-to)42-44
Number of pages3
JournalIEEE Microwave and Wireless Components Letters
Issue number1
Publication statusPublished - 2009 Jan 1



  • 24 GHz
  • CMOS
  • Fully integrated
  • Power amplifier (PA)

ASJC Scopus subject areas

  • Condensed Matter Physics
  • Electrical and Electronic Engineering

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