A 14-nm FinFET Logic CMOS Process Compatible RRAM Flash with Excellent Immunity to Sneak Path

E. Ray Hsieh, Yen Chen Kuo, Chih Hung Cheng, Jing Ling Kuo, Meng Ru Jiang, Jian Li Lin, Hung Wen Chen, Steve S. Chung, Chuan Hsi Liu, Tse Pu Chen, Shih An Huang, Tai Ju Chen, Osbert Cheng

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

In this paper, we have demonstrated an oxygen-vacancy-based bipolar RRAM on a pure logic 14-nm-node HKMG FinFET platform. A unit cell of the memory consists of a control transistor (FinFET) and a storage transistor (a second FinFET). The later performs as a bipolar RRAM. This unit cell can be integrated in an AND-type memory array. The memory cell has an ON/OFF ratio equal to 200 and 400 for the n-type and p-type FinFET RRAMs, respectively, endurance larger than 400 and 1000 times for n- and p-type devices, respectively, and the retention test for over 1 month under 125 °C temperature environment. To analyze the array performance of the AND-type FinFET RRAM at the circuit level, we have further discussed the issues of the sneak path and disturbance, in which an active-fin isolation of FinFET in an AND-type array has been suggested to minimize the leakage current induced by sneak paths. The results have shown a large window with up to 10 3 ON/OFF ratio, 30% standby power reduction, and 90% active power reduction with reference to the conventional AND-type array. As a result, the bipolar FinFET RRAM exhibits great potential for the embedded memory applications, in particular it can be extended to 28-nm HKMG and the FinFET platform beyond 14-nm technology node, to fill the Moore's gap between the high-performance logic and the embedded memory.

Original languageEnglish
Article number8089812
Pages (from-to)4910-4918
Number of pages9
JournalIEEE Transactions on Electron Devices
Volume64
Issue number12
DOIs
Publication statusPublished - 2017 Dec 1

Fingerprint

Data storage equipment
Transistors
RRAM
FinFET
Oxygen vacancies
Leakage currents
Durability
Networks (circuits)
Temperature

Keywords

  • Embedded memory
  • FinFET
  • high-k metal gate
  • Moore's gap
  • RRAM
  • sneak path

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Hsieh, E. R., Kuo, Y. C., Cheng, C. H., Kuo, J. L., Jiang, M. R., Lin, J. L., ... Cheng, O. (2017). A 14-nm FinFET Logic CMOS Process Compatible RRAM Flash with Excellent Immunity to Sneak Path. IEEE Transactions on Electron Devices, 64(12), 4910-4918. [8089812]. https://doi.org/10.1109/TED.2017.2763960

A 14-nm FinFET Logic CMOS Process Compatible RRAM Flash with Excellent Immunity to Sneak Path. / Hsieh, E. Ray; Kuo, Yen Chen; Cheng, Chih Hung; Kuo, Jing Ling; Jiang, Meng Ru; Lin, Jian Li; Chen, Hung Wen; Chung, Steve S.; Liu, Chuan Hsi; Chen, Tse Pu; Huang, Shih An; Chen, Tai Ju; Cheng, Osbert.

In: IEEE Transactions on Electron Devices, Vol. 64, No. 12, 8089812, 01.12.2017, p. 4910-4918.

Research output: Contribution to journalArticle

Hsieh, ER, Kuo, YC, Cheng, CH, Kuo, JL, Jiang, MR, Lin, JL, Chen, HW, Chung, SS, Liu, CH, Chen, TP, Huang, SA, Chen, TJ & Cheng, O 2017, 'A 14-nm FinFET Logic CMOS Process Compatible RRAM Flash with Excellent Immunity to Sneak Path', IEEE Transactions on Electron Devices, vol. 64, no. 12, 8089812, pp. 4910-4918. https://doi.org/10.1109/TED.2017.2763960
Hsieh, E. Ray ; Kuo, Yen Chen ; Cheng, Chih Hung ; Kuo, Jing Ling ; Jiang, Meng Ru ; Lin, Jian Li ; Chen, Hung Wen ; Chung, Steve S. ; Liu, Chuan Hsi ; Chen, Tse Pu ; Huang, Shih An ; Chen, Tai Ju ; Cheng, Osbert. / A 14-nm FinFET Logic CMOS Process Compatible RRAM Flash with Excellent Immunity to Sneak Path. In: IEEE Transactions on Electron Devices. 2017 ; Vol. 64, No. 12. pp. 4910-4918.
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AU - Jiang, Meng Ru

AU - Lin, Jian Li

AU - Chen, Hung Wen

AU - Chung, Steve S.

AU - Liu, Chuan Hsi

AU - Chen, Tse Pu

AU - Huang, Shih An

AU - Chen, Tai Ju

AU - Cheng, Osbert

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