A 128-phase delay-locked loop with cyclic VCDL

Chien Hung Kuo, Yu Chieh Ma

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

A multiphase delay-locked loop with cyclic voltage controlled delay line is presented in this paper. The 128 output phases can be simultaneously produced by the 16-delay units of VCDL. The presented multi-phase DLL is realized by CMOS 90 nm 1P9M process. The total power consumption is 9.2 mW at the supply voltage of 1.2 V and the operational frequency of 92.16 MHz.

Original languageEnglish
Title of host publicationProceedings of the 5th Asia Symposium on Quality Electronic Design, ASQED 2013
PublisherIEEE Computer Society
Pages10-13
Number of pages4
ISBN (Print)9781479913145
DOIs
Publication statusPublished - 2013 Jan 1
Event5th Asia Symposium on Quality Electronic Design, ASQED 2013 - Penang, Malaysia
Duration: 2013 Aug 262013 Aug 28

Publication series

NameProceedings of the 5th Asia Symposium on Quality Electronic Design, ASQED 2013

Other

Other5th Asia Symposium on Quality Electronic Design, ASQED 2013
CountryMalaysia
CityPenang
Period13/8/2613/8/28

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Keywords

  • Clock generator
  • Cyclic VCDL
  • Multi-phase DLL

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

Cite this

Kuo, C. H., & Ma, Y. C. (2013). A 128-phase delay-locked loop with cyclic VCDL. In Proceedings of the 5th Asia Symposium on Quality Electronic Design, ASQED 2013 (pp. 10-13). [6643555] (Proceedings of the 5th Asia Symposium on Quality Electronic Design, ASQED 2013). IEEE Computer Society. https://doi.org/10.1109/ASQED.2013.6643555