A 1-V 10.7-MHz fourth-order bandpass ΔΣ modulators using two switched opamps

Chien Hung Kuo, Shen Iuan Liu

Research output: Contribution to journalArticle

12 Citations (Scopus)

Abstract

A 1-V 10.7-MHz fourth-order bandpass delta-sigma modulator using two switched opamps (SOPs) is presented. The 3/4 sampling frequency and the double-sampling techniques are adapted for this modulator to relax the required clocking rate. The presented modulator can not only reduce the number of SOPs, but also the number of capacitors. It has been implemented in 0.25-μm 1P5M CMOS process with MIM capacitors. The modulator can receive 10.7-MHz IF signals by using a clock frequency of 7.13 MHz. A dynamic range of 62 dB within bandwidth of 200 kHz is achieved and the power consumption of 8.45 mW is measured at 1-V supply voltage. The image tone can be suppressed by 44 dB with respect to the carrier. The in-band third-order intermodulation (IM3) distortion is -65 dBc below the desired signal.

Original languageEnglish
Pages (from-to)2041-2045
Number of pages5
JournalIEEE Journal of Solid-State Circuits
Volume39
Issue number11
DOIs
Publication statusPublished - 2004 Nov 1

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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