8-bit AES implementation in FPGA by multiplexing 32-bit AES operation

Chi Jeng Chang; Chi Wu Huang; Hung Yun Tai; Mao Yuan Lin

doi:10.1109/ISDPE.2007.131

8-bit AES implementation in FPGA by multiplexing 32-bit AES operation

Chi Jeng Chang^*, Chi Wu Huang, Hung Yun Tai, Mao Yuan Lin

^*Corresponding author for this work

Department of Industrial Education

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Citations (Scopus)

Abstract

8-bit AES implementation was first proposed by Tim Good[8] as Application-Specific-Instruction-Process(ASIP), featured in low area design based on the stored-program design concept, which the software programs runs in a hardware processor. This paper proposes a direct hardware implementation of AES algorithm. There are two kinds of implementation, one uses shift registers for KeyExpansion and Mixcolumn called Shift-type, the other called BRAM-type uses Block RAMs (BRAMs) instead of shift registers. Both Implementations gain much higher throughput than ASIP. However, BRAM-type uses only 130 slices and achieves a throughput of 27 Mega bit per second (Mbps). Comparing to ASIP's 122 slices and 2.18 Mbps throughput, it achieves 12 times increase in throughput, 8% increase in slice number and no software programming necessary.

Original language	English
Title of host publication	Proceedings of the 1st International Symposium on Data, Privacy, and E-Commerce, ISDPE 2007
Pages	505-507
Number of pages	3
DOIs	https://doi.org/10.1109/ISDPE.2007.131
Publication status	Published - 2007
Event	1st International Symposium on Data, Privacy, and E-Commerce, ISDPE 2007 - Chengdu, China Duration: 2007 Nov 1 → 2007 Nov 3

Publication series

Name	Proceedings of the 1st International Symposium on Data, Privacy, and E-Commerce, ISDPE 2007

Conference

Conference	1st International Symposium on Data, Privacy, and E-Commerce, ISDPE 2007
Country/Territory	China
City	Chengdu
Period	2007/11/01 → 2007/11/03

ASJC Scopus subject areas

General Computer Science
Economics, Econometrics and Finance (miscellaneous)

Access to Document

10.1109/ISDPE.2007.131

Cite this

Chang, C. J., Huang, C. W., Tai, H. Y., & Lin, M. Y. (2007). 8-bit AES implementation in FPGA by multiplexing 32-bit AES operation. In Proceedings of the 1st International Symposium on Data, Privacy, and E-Commerce, ISDPE 2007 (pp. 505-507). Article 4402744 (Proceedings of the 1st International Symposium on Data, Privacy, and E-Commerce, ISDPE 2007). https://doi.org/10.1109/ISDPE.2007.131

8-bit AES implementation in FPGA by multiplexing 32-bit AES operation. / Chang, Chi Jeng; Huang, Chi Wu; Tai, Hung Yun et al.
Proceedings of the 1st International Symposium on Data, Privacy, and E-Commerce, ISDPE 2007. 2007. p. 505-507 4402744 (Proceedings of the 1st International Symposium on Data, Privacy, and E-Commerce, ISDPE 2007).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Chang, CJ, Huang, CW, Tai, HY & Lin, MY 2007, 8-bit AES implementation in FPGA by multiplexing 32-bit AES operation. in Proceedings of the 1st International Symposium on Data, Privacy, and E-Commerce, ISDPE 2007., 4402744, Proceedings of the 1st International Symposium on Data, Privacy, and E-Commerce, ISDPE 2007, pp. 505-507, 1st International Symposium on Data, Privacy, and E-Commerce, ISDPE 2007, Chengdu, China, 2007/11/01. https://doi.org/10.1109/ISDPE.2007.131

@inproceedings{b7400de8dc9d4428938f39f45ee4a999,

title = "8-bit AES implementation in FPGA by multiplexing 32-bit AES operation",

abstract = "8-bit AES implementation was first proposed by Tim Good[8] as Application-Specific-Instruction-Process(ASIP), featured in low area design based on the stored-program design concept, which the software programs runs in a hardware processor. This paper proposes a direct hardware implementation of AES algorithm. There are two kinds of implementation, one uses shift registers for KeyExpansion and Mixcolumn called Shift-type, the other called BRAM-type uses Block RAMs (BRAMs) instead of shift registers. Both Implementations gain much higher throughput than ASIP. However, BRAM-type uses only 130 slices and achieves a throughput of 27 Mega bit per second (Mbps). Comparing to ASIP's 122 slices and 2.18 Mbps throughput, it achieves 12 times increase in throughput, 8% increase in slice number and no software programming necessary.",

author = "Chang, {Chi Jeng} and Huang, {Chi Wu} and Tai, {Hung Yun} and Lin, {Mao Yuan}",

year = "2007",

doi = "10.1109/ISDPE.2007.131",

language = "English",

isbn = "0769530168",

series = "Proceedings of the 1st International Symposium on Data, Privacy, and E-Commerce, ISDPE 2007",

pages = "505--507",

booktitle = "Proceedings of the 1st International Symposium on Data, Privacy, and E-Commerce, ISDPE 2007",

note = "1st International Symposium on Data, Privacy, and E-Commerce, ISDPE 2007 ; Conference date: 01-11-2007 Through 03-11-2007",

}

TY - GEN

T1 - 8-bit AES implementation in FPGA by multiplexing 32-bit AES operation

AU - Chang, Chi Jeng

AU - Huang, Chi Wu

AU - Tai, Hung Yun

AU - Lin, Mao Yuan

PY - 2007

Y1 - 2007

N2 - 8-bit AES implementation was first proposed by Tim Good[8] as Application-Specific-Instruction-Process(ASIP), featured in low area design based on the stored-program design concept, which the software programs runs in a hardware processor. This paper proposes a direct hardware implementation of AES algorithm. There are two kinds of implementation, one uses shift registers for KeyExpansion and Mixcolumn called Shift-type, the other called BRAM-type uses Block RAMs (BRAMs) instead of shift registers. Both Implementations gain much higher throughput than ASIP. However, BRAM-type uses only 130 slices and achieves a throughput of 27 Mega bit per second (Mbps). Comparing to ASIP's 122 slices and 2.18 Mbps throughput, it achieves 12 times increase in throughput, 8% increase in slice number and no software programming necessary.

AB - 8-bit AES implementation was first proposed by Tim Good[8] as Application-Specific-Instruction-Process(ASIP), featured in low area design based on the stored-program design concept, which the software programs runs in a hardware processor. This paper proposes a direct hardware implementation of AES algorithm. There are two kinds of implementation, one uses shift registers for KeyExpansion and Mixcolumn called Shift-type, the other called BRAM-type uses Block RAMs (BRAMs) instead of shift registers. Both Implementations gain much higher throughput than ASIP. However, BRAM-type uses only 130 slices and achieves a throughput of 27 Mega bit per second (Mbps). Comparing to ASIP's 122 slices and 2.18 Mbps throughput, it achieves 12 times increase in throughput, 8% increase in slice number and no software programming necessary.

UR - http://www.scopus.com/inward/record.url?scp=48049116855&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=48049116855&partnerID=8YFLogxK

U2 - 10.1109/ISDPE.2007.131

DO - 10.1109/ISDPE.2007.131

M3 - Conference contribution

AN - SCOPUS:48049116855

SN - 0769530168

SN - 9780769530161

T3 - Proceedings of the 1st International Symposium on Data, Privacy, and E-Commerce, ISDPE 2007

SP - 505

EP - 507

BT - Proceedings of the 1st International Symposium on Data, Privacy, and E-Commerce, ISDPE 2007

T2 - 1st International Symposium on Data, Privacy, and E-Commerce, ISDPE 2007

Y2 - 1 November 2007 through 3 November 2007

ER -

8-bit AES implementation in FPGA by multiplexing 32-bit AES operation

Abstract

Publication series

Conference

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this