8-bit AES FPGA implementation using block RAM

Chi Jeng Chang*, Chi Wu Huang, Hung Yun Tai, Mao Yuan Lin, Teng Kuei Hu

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

14 Citations (Scopus)


An 8-bit data-path AES implementation was proposed recently by Tim Good [1] as Application-Specific-Instruction-Processor (ASIP) for the increasing popular applications in PDA, wireless network and embedded devices. This paper proposes an 8-bit AES implementation design that keeps MixColumn and sequential controls for AES operation in the processing area while moving the circuit necessary for other operations such as Sbox, ShiftRow and KeyExpansion to Block RAMs (BRAMs) of Xilinx FPGA chip. Thus, it keeps the low resource area around 130 slices uses 4 BRAMs and achieves 27 Megabit per second (Mbps) throughput. Our design obtains approximately 12 times (1200%) increase in throughput with 8% increase in resource area comparing to the ASIP instruction set design approach of 8-bit AES processor proposed in 2006.

Original languageEnglish
Title of host publicationProceedings of the 33rd Annual Conference of the IEEE Industrial Electronics Society, IECON
Number of pages6
Publication statusPublished - 2007
Event33rd Annual Conference of the IEEE Industrial Electronics Society, IECON - Taipei, Taiwan
Duration: 2007 Nov 52007 Nov 8

Publication series

NameIECON Proceedings (Industrial Electronics Conference)


Other33rd Annual Conference of the IEEE Industrial Electronics Society, IECON


  • AES
  • Application-specific instruction processor(ASIP)
  • Block RAM (BRAM)
  • FPGA
  • Small area

ASJC Scopus subject areas

  • Control and Systems Engineering
  • Electrical and Electronic Engineering


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