8-bit AES FPGA implementation using block RAM

Chi Jeng Chang; Chi Wu Huang; Hung Yun Tai; Mao Yuan Lin; Teng Kuei Hu

doi:10.1109/IECON.2007.4460363

8-bit AES FPGA implementation using block RAM

Chi Jeng Chang, Chi Wu Huang, Hung Yun Tai, Mao Yuan Lin, Teng Kuei Hu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

13 Citations (Scopus)

Abstract

An 8-bit data-path AES implementation was proposed recently by Tim Good [1] as Application-Specific-Instruction-Processor (ASIP) for the increasing popular applications in PDA, wireless network and embedded devices. This paper proposes an 8-bit AES implementation design that keeps MixColumn and sequential controls for AES operation in the processing area while moving the circuit necessary for other operations such as Sbox, ShiftRow and KeyExpansion to Block RAMs (BRAMs) of Xilinx FPGA chip. Thus, it keeps the low resource area around 130 slices uses 4 BRAMs and achieves 27 Megabit per second (Mbps) throughput. Our design obtains approximately 12 times (1200%) increase in throughput with 8% increase in resource area comparing to the ASIP instruction set design approach of 8-bit AES processor proposed in 2006.

Original language	English
Title of host publication	Proceedings of the 33rd Annual Conference of the IEEE Industrial Electronics Society, IECON
Pages	2654-2659
Number of pages	6
DOIs	https://doi.org/10.1109/IECON.2007.4460363
Publication status	Published - 2007
Event	33rd Annual Conference of the IEEE Industrial Electronics Society, IECON - Taipei, Taiwan Duration: 2007 Nov 5 → 2007 Nov 8

Other

Other	33rd Annual Conference of the IEEE Industrial Electronics Society, IECON
Country	Taiwan
City	Taipei
Period	07/11/5 → 07/11/8

Keywords

AES
Application-specific instruction processor(ASIP)
Block RAM (BRAM)
FPGA
Small area

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/IECON.2007.4460363

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Cite this

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title = "8-bit AES FPGA implementation using block RAM",

abstract = "An 8-bit data-path AES implementation was proposed recently by Tim Good [1] as Application-Specific-Instruction-Processor (ASIP) for the increasing popular applications in PDA, wireless network and embedded devices. This paper proposes an 8-bit AES implementation design that keeps MixColumn and sequential controls for AES operation in the processing area while moving the circuit necessary for other operations such as Sbox, ShiftRow and KeyExpansion to Block RAMs (BRAMs) of Xilinx FPGA chip. Thus, it keeps the low resource area around 130 slices uses 4 BRAMs and achieves 27 Megabit per second (Mbps) throughput. Our design obtains approximately 12 times (1200%) increase in throughput with 8% increase in resource area comparing to the ASIP instruction set design approach of 8-bit AES processor proposed in 2006.",

keywords = "AES, Application-specific instruction processor(ASIP), Block RAM (BRAM), FPGA, Small area",

author = "Chang, {Chi Jeng} and Huang, {Chi Wu} and Tai, {Hung Yun} and Lin, {Mao Yuan} and Hu, {Teng Kuei}",

year = "2007",

doi = "10.1109/IECON.2007.4460363",

language = "English",

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pages = "2654--2659",

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note = "33rd Annual Conference of the IEEE Industrial Electronics Society, IECON ; Conference date: 05-11-2007 Through 08-11-2007",

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AU - Huang, Chi Wu

AU - Tai, Hung Yun

AU - Lin, Mao Yuan

AU - Hu, Teng Kuei

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N2 - An 8-bit data-path AES implementation was proposed recently by Tim Good [1] as Application-Specific-Instruction-Processor (ASIP) for the increasing popular applications in PDA, wireless network and embedded devices. This paper proposes an 8-bit AES implementation design that keeps MixColumn and sequential controls for AES operation in the processing area while moving the circuit necessary for other operations such as Sbox, ShiftRow and KeyExpansion to Block RAMs (BRAMs) of Xilinx FPGA chip. Thus, it keeps the low resource area around 130 slices uses 4 BRAMs and achieves 27 Megabit per second (Mbps) throughput. Our design obtains approximately 12 times (1200%) increase in throughput with 8% increase in resource area comparing to the ASIP instruction set design approach of 8-bit AES processor proposed in 2006.

AB - An 8-bit data-path AES implementation was proposed recently by Tim Good [1] as Application-Specific-Instruction-Processor (ASIP) for the increasing popular applications in PDA, wireless network and embedded devices. This paper proposes an 8-bit AES implementation design that keeps MixColumn and sequential controls for AES operation in the processing area while moving the circuit necessary for other operations such as Sbox, ShiftRow and KeyExpansion to Block RAMs (BRAMs) of Xilinx FPGA chip. Thus, it keeps the low resource area around 130 slices uses 4 BRAMs and achieves 27 Megabit per second (Mbps) throughput. Our design obtains approximately 12 times (1200%) increase in throughput with 8% increase in resource area comparing to the ASIP instruction set design approach of 8-bit AES processor proposed in 2006.

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KW - Block RAM (BRAM)

KW - FPGA

KW - Small area

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