Abstract
An 8-bit data-path AES implementation was proposed recently by Tim Good [1] as Application-Specific-Instruction-Processor (ASIP) for the increasing popular applications in PDA, wireless network and embedded devices. This paper proposes an 8-bit AES implementation design that keeps MixColumn and sequential controls for AES operation in the processing area while moving the circuit necessary for other operations such as Sbox, ShiftRow and KeyExpansion to Block RAMs (BRAMs) of Xilinx FPGA chip. Thus, it keeps the low resource area around 130 slices uses 4 BRAMs and achieves 27 Megabit per second (Mbps) throughput. Our design obtains approximately 12 times (1200%) increase in throughput with 8% increase in resource area comparing to the ASIP instruction set design approach of 8-bit AES processor proposed in 2006.
| Original language | English |
|---|---|
| Title of host publication | Proceedings of the 33rd Annual Conference of the IEEE Industrial Electronics Society, IECON |
| Pages | 2654-2659 |
| Number of pages | 6 |
| DOIs | |
| Publication status | Published - 2007 |
| Event | 33rd Annual Conference of the IEEE Industrial Electronics Society, IECON - Taipei, Taiwan Duration: 2007 Nov 5 → 2007 Nov 8 |
Other
| Other | 33rd Annual Conference of the IEEE Industrial Electronics Society, IECON |
|---|---|
| Country | Taiwan |
| City | Taipei |
| Period | 07/11/5 → 07/11/8 |
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Keywords
- AES
- Application-specific instruction processor(ASIP)
- Block RAM (BRAM)
- FPGA
- Small area
ASJC Scopus subject areas
- Electrical and Electronic Engineering
Cite this
8-bit AES FPGA implementation using block RAM. / Chang, Chi Jeng; Huang, Chi Wu; Tai, Hung Yun; Lin, Mao Yuan; Hu, Teng Kuei.
Proceedings of the 33rd Annual Conference of the IEEE Industrial Electronics Society, IECON. 2007. p. 2654-2659 4460363.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - 8-bit AES FPGA implementation using block RAM
AU - Chang, Chi Jeng
AU - Huang, Chi Wu
AU - Tai, Hung Yun
AU - Lin, Mao Yuan
AU - Hu, Teng Kuei
PY - 2007
Y1 - 2007
N2 - An 8-bit data-path AES implementation was proposed recently by Tim Good [1] as Application-Specific-Instruction-Processor (ASIP) for the increasing popular applications in PDA, wireless network and embedded devices. This paper proposes an 8-bit AES implementation design that keeps MixColumn and sequential controls for AES operation in the processing area while moving the circuit necessary for other operations such as Sbox, ShiftRow and KeyExpansion to Block RAMs (BRAMs) of Xilinx FPGA chip. Thus, it keeps the low resource area around 130 slices uses 4 BRAMs and achieves 27 Megabit per second (Mbps) throughput. Our design obtains approximately 12 times (1200%) increase in throughput with 8% increase in resource area comparing to the ASIP instruction set design approach of 8-bit AES processor proposed in 2006.
AB - An 8-bit data-path AES implementation was proposed recently by Tim Good [1] as Application-Specific-Instruction-Processor (ASIP) for the increasing popular applications in PDA, wireless network and embedded devices. This paper proposes an 8-bit AES implementation design that keeps MixColumn and sequential controls for AES operation in the processing area while moving the circuit necessary for other operations such as Sbox, ShiftRow and KeyExpansion to Block RAMs (BRAMs) of Xilinx FPGA chip. Thus, it keeps the low resource area around 130 slices uses 4 BRAMs and achieves 27 Megabit per second (Mbps) throughput. Our design obtains approximately 12 times (1200%) increase in throughput with 8% increase in resource area comparing to the ASIP instruction set design approach of 8-bit AES processor proposed in 2006.
KW - AES
KW - Application-specific instruction processor(ASIP)
KW - Block RAM (BRAM)
KW - FPGA
KW - Small area
UR - http://www.scopus.com/inward/record.url?scp=49949105743&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=49949105743&partnerID=8YFLogxK
U2 - 10.1109/IECON.2007.4460363
DO - 10.1109/IECON.2007.4460363
M3 - Conference contribution
AN - SCOPUS:49949105743
SN - 1424407834
SN - 9781424407835
SP - 2654
EP - 2659
BT - Proceedings of the 33rd Annual Conference of the IEEE Industrial Electronics Society, IECON
ER -