5.3 GHz 42% PAE class-E power amplifier with 532 mW/mm2 power area density in 180 nm CMOS process

H. Alsuraisry; M. H. Wu; P. S. Huang; J. H. Tsai; T. W. Huang

doi:10.1049/el.2016.1629

5.3 GHz 42% PAE class-E power amplifier with 532 mW/mm² power area density in 180 nm CMOS process

H. Alsuraisry, M. H. Wu, P. S. Huang, J. H. Tsai, T. W. Huang^*

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

6 Citations (Scopus)

Abstract

A 5.3 GHz high-efficiency and low-cost class-E power amplifier (PA) implemented in a 180 nm CMOS process is presented. Cascode con- figuration is utilised in the class-E PA to achieve high efficiency due to its high gain property and low drain-to-source parasitic capacitor. Through the trade-off between inductance and inductor loss, an optimised RF choke inductor for fully integrated class-E PA design can be selected to achieve high efficiency while maintaining compact circuit size. The class-E CMOS PA demonstrates the highest Power Added Efficiency (PAE) of 42% and greatest power area density of 532 mW/mm² in 0.263 mm² chip area to date.

Original language	English
Pages (from-to)	1338-1340
Number of pages	3
Journal	Electronics Letters
Volume	52
Issue number	15
DOIs	https://doi.org/10.1049/el.2016.1629
Publication status	Published - 2016 Jul 21
Externally published	Yes

ASJC Scopus subject areas

Electrical and Electronic Engineering

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title = "5.3 GHz 42% PAE class-E power amplifier with 532 mW/mm2 power area density in 180 nm CMOS process",

abstract = "A 5.3 GHz high-efficiency and low-cost class-E power amplifier (PA) implemented in a 180 nm CMOS process is presented. Cascode con- figuration is utilised in the class-E PA to achieve high efficiency due to its high gain property and low drain-to-source parasitic capacitor. Through the trade-off between inductance and inductor loss, an optimised RF choke inductor for fully integrated class-E PA design can be selected to achieve high efficiency while maintaining compact circuit size. The class-E CMOS PA demonstrates the highest Power Added Efficiency (PAE) of 42% and greatest power area density of 532 mW/mm2 in 0.263 mm2 chip area to date.",

author = "H. Alsuraisry and Wu, {M. H.} and Huang, {P. S.} and Tsai, {J. H.} and Huang, {T. W.}",

note = "Funding Information: This work was supported in part by the Ministry of Science and Technology (MOST) under contract MOST 104-3115-E-002-006, contract MOST 104-3115-E-002-003, contract MOST 104-2221-E-002-056, contract NSC 102-2221-E-002-038-MY3, 105R8908 and 105R890834. Publisher Copyright: {\textcopyright} 2016 The Institution of Engineering and Technology.",

year = "2016",

month = jul,

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doi = "10.1049/el.2016.1629",

language = "English",

volume = "52",

pages = "1338--1340",

journal = "Electronics Letters",

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AU - Alsuraisry, H.

AU - Wu, M. H.

AU - Huang, P. S.

AU - Tsai, J. H.

AU - Huang, T. W.

N1 - Funding Information: This work was supported in part by the Ministry of Science and Technology (MOST) under contract MOST 104-3115-E-002-006, contract MOST 104-3115-E-002-003, contract MOST 104-2221-E-002-056, contract NSC 102-2221-E-002-038-MY3, 105R8908 and 105R890834. Publisher Copyright: © 2016 The Institution of Engineering and Technology.

PY - 2016/7/21

Y1 - 2016/7/21

N2 - A 5.3 GHz high-efficiency and low-cost class-E power amplifier (PA) implemented in a 180 nm CMOS process is presented. Cascode con- figuration is utilised in the class-E PA to achieve high efficiency due to its high gain property and low drain-to-source parasitic capacitor. Through the trade-off between inductance and inductor loss, an optimised RF choke inductor for fully integrated class-E PA design can be selected to achieve high efficiency while maintaining compact circuit size. The class-E CMOS PA demonstrates the highest Power Added Efficiency (PAE) of 42% and greatest power area density of 532 mW/mm2 in 0.263 mm2 chip area to date.

AB - A 5.3 GHz high-efficiency and low-cost class-E power amplifier (PA) implemented in a 180 nm CMOS process is presented. Cascode con- figuration is utilised in the class-E PA to achieve high efficiency due to its high gain property and low drain-to-source parasitic capacitor. Through the trade-off between inductance and inductor loss, an optimised RF choke inductor for fully integrated class-E PA design can be selected to achieve high efficiency while maintaining compact circuit size. The class-E CMOS PA demonstrates the highest Power Added Efficiency (PAE) of 42% and greatest power area density of 532 mW/mm2 in 0.263 mm2 chip area to date.

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5.3 GHz 42% PAE class-E power amplifier with 532 mW/mm² power area density in 180 nm CMOS process

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