5.3 GHz 42% PAE class-E power amplifier with 532 mW/mm2 power area density in 180 nm CMOS process

H. Alsuraisry, M. H. Wu, P. S. Huang, J. H. Tsai, T. W. Huang

Research output: Contribution to journalArticle

3 Citations (Scopus)

Abstract

A 5.3 GHz high-efficiency and low-cost class-E power amplifier (PA) implemented in a 180 nm CMOS process is presented. Cascode con- figuration is utilised in the class-E PA to achieve high efficiency due to its high gain property and low drain-to-source parasitic capacitor. Through the trade-off between inductance and inductor loss, an optimised RF choke inductor for fully integrated class-E PA design can be selected to achieve high efficiency while maintaining compact circuit size. The class-E CMOS PA demonstrates the highest Power Added Efficiency (PAE) of 42% and greatest power area density of 532 mW/mm2 in 0.263 mm2 chip area to date.

Original languageEnglish
Pages (from-to)1338-1340
Number of pages3
JournalElectronics Letters
Volume52
Issue number15
DOIs
Publication statusPublished - 2016 Jul 21

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Power amplifiers
Electric inductors
Inductance
Capacitors
Networks (circuits)
Costs

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

5.3 GHz 42% PAE class-E power amplifier with 532 mW/mm2 power area density in 180 nm CMOS process. / Alsuraisry, H.; Wu, M. H.; Huang, P. S.; Tsai, J. H.; Huang, T. W.

In: Electronics Letters, Vol. 52, No. 15, 21.07.2016, p. 1338-1340.

Research output: Contribution to journalArticle

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