3xVDD-tolerant power-rail ESD clamp circuit for negative mixed-voltage interfaces

Hao En Cheng; Ching Lin Wu; Chun Yu Lin

doi:10.1016/j.sse.2025.109185

3xVDD-tolerant power-rail ESD clamp circuit for negative mixed-voltage interfaces

Hao En Cheng
, Ching Lin Wu
, Chun Yu Lin^*

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

Abstract

In this article, a novel power-rail ESD clamp circuit for negative voltage power pins has been proposed and fabricated in a 0.18-μm 1.8-V CMOS process. The proposed circuit, implemented using only 1.8-V nMOS/pMOS devices, achieves a voltage tolerance of 3xVDD (5.4 V), surpassing the 2xVDD-tolerance of most existing designs. Additionally, the circuit demonstrates HBM robustness of over 8 kV and exhibits an exceptionally low leakage current of approximately 0.7nA at room temperature, making it highly suitable for negative voltage environments in biomedical circuits, mixed-voltage applications, and power management systems.

Original language	English
Article number	109185
Journal	Solid-State Electronics
Volume	229
DOIs	https://doi.org/10.1016/j.sse.2025.109185
Publication status	Published - 2025 Nov
Externally published	Yes

Keywords

ESD protection circuit
Mixed-voltage interface
Negative voltage supply

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Materials Chemistry
Electrical and Electronic Engineering

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10.1016/j.sse.2025.109185

Cite this

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title = "3xVDD-tolerant power-rail ESD clamp circuit for negative mixed-voltage interfaces",

abstract = "In this article, a novel power-rail ESD clamp circuit for negative voltage power pins has been proposed and fabricated in a 0.18-μm 1.8-V CMOS process. The proposed circuit, implemented using only 1.8-V nMOS/pMOS devices, achieves a voltage tolerance of 3xVDD (5.4 V), surpassing the 2xVDD-tolerance of most existing designs. Additionally, the circuit demonstrates HBM robustness of over 8 kV and exhibits an exceptionally low leakage current of approximately 0.7nA at room temperature, making it highly suitable for negative voltage environments in biomedical circuits, mixed-voltage applications, and power management systems.",

keywords = "ESD protection circuit, Mixed-voltage interface, Negative voltage supply",

author = "Cheng, \{Hao En\} and Wu, \{Ching Lin\} and Lin, \{Chun Yu\}",

note = "Publisher Copyright: {\textcopyright} 2025 Elsevier Ltd",

year = "2025",

month = nov,

doi = "10.1016/j.sse.2025.109185",

language = "English",

volume = "229",

journal = "Solid-State Electronics",

issn = "0038-1101",

publisher = "Elsevier Limited",

}

TY - JOUR

T1 - 3xVDD-tolerant power-rail ESD clamp circuit for negative mixed-voltage interfaces

AU - Cheng, Hao En

AU - Wu, Ching Lin

AU - Lin, Chun Yu

PY - 2025/11

Y1 - 2025/11

N2 - In this article, a novel power-rail ESD clamp circuit for negative voltage power pins has been proposed and fabricated in a 0.18-μm 1.8-V CMOS process. The proposed circuit, implemented using only 1.8-V nMOS/pMOS devices, achieves a voltage tolerance of 3xVDD (5.4 V), surpassing the 2xVDD-tolerance of most existing designs. Additionally, the circuit demonstrates HBM robustness of over 8 kV and exhibits an exceptionally low leakage current of approximately 0.7nA at room temperature, making it highly suitable for negative voltage environments in biomedical circuits, mixed-voltage applications, and power management systems.

AB - In this article, a novel power-rail ESD clamp circuit for negative voltage power pins has been proposed and fabricated in a 0.18-μm 1.8-V CMOS process. The proposed circuit, implemented using only 1.8-V nMOS/pMOS devices, achieves a voltage tolerance of 3xVDD (5.4 V), surpassing the 2xVDD-tolerance of most existing designs. Additionally, the circuit demonstrates HBM robustness of over 8 kV and exhibits an exceptionally low leakage current of approximately 0.7nA at room temperature, making it highly suitable for negative voltage environments in biomedical circuits, mixed-voltage applications, and power management systems.

KW - ESD protection circuit

KW - Mixed-voltage interface

KW - Negative voltage supply

UR - https://www.scopus.com/pages/publications/105008793795

UR - https://www.scopus.com/pages/publications/105008793795#tab=citedBy

U2 - 10.1016/j.sse.2025.109185

DO - 10.1016/j.sse.2025.109185

M3 - Article

AN - SCOPUS:105008793795

SN - 0038-1101

VL - 229

JO - Solid-State Electronics

JF - Solid-State Electronics

M1 - 109185

ER -

3xVDD-tolerant power-rail ESD clamp circuit for negative mixed-voltage interfaces

Abstract

Keywords

ASJC Scopus subject areas

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