3-D Vertical Ferroelectric FETs for Nonvolatile Memory Design With Prolonged Retention Mechanism and Triple-Level Cell (TLC) by Voltage/Width Modulation

A nonvolatile ferroelectric DRAM (FeDRAM) architecture is experimentally demonstrated using 3-D vertical poly-Si ferroelectric FETs (FeFETs) as vertically stackable memory cells for read functionality and a back-end-of-line (BEOL) W:In₂O₃ (IWO) FET as a write transistor. The vertical FeFETs exhibit a practical memory window (MW) of 2.63 V with a stable data retention time exceeding 10⁴ s and robust endurance, achieving 10⁸ program/erase cycles. The proposed architecture demonstrates enhanced data retention by leveraging the storage node (SN) to suppress the depolarization field and improve dipole stability while enabling a 0-V standby to improve energy efficiency. The triple-level cell (TLC) operation access can be achieved using pulse amplitude or pulsewidth modulation of program/erase (PG/ER) signals. The 3-D-integrated architecture of the vertical FeFET demonstrates its promising capacity for high-density memory applications while maintaining compatibility with the mature CMOS industry.