2 X VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65-nm CMOS process

Chun Yu Lin; Ming Dou Ker

doi:10.1109/ISCAS.2010.5537864

2 X VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65-nm CMOS process

Chun Yu Lin^*, Ming Dou Ker

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

With the consideration of low standby leakage in nanoscale CMOS processes, a new 2xVDD-tolerant ESD clamp circuit was presented in this paper. The new ESD clamp circuit had a high-voltage-tolerant ESD detection circuit to improve the turn-on efficiency of the silicon-controlled-rectifier-based (SCR-based) ESD device. This design had been successfully verified in a 65-nm CMOS process. The leakage current of this ESD clamp circuit under normal circuit operating condition was only ∼200 nA. Besides, this ESD clamp circuit can achieve 4.8-kV HBM ESD robustness. Therefore, this design was very suitable for mixed-voltage I/O interfaces in nanoscale CMOS processes.

Original language	English
Title of host publication	ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems
Subtitle of host publication	Nano-Bio Circuit Fabrics and Systems
Pages	3417-3420
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2010.5537864
Publication status	Published - 2010
Externally published	Yes
Event	2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010 - Paris, France Duration: 2010 May 30 → 2010 Jun 2

Publication series

Name	ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems

Other

Other	2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010
Country/Territory	France
City	Paris
Period	2010/05/30 → 2010/06/02

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ISCAS.2010.5537864

Cite this

Lin, C. Y., & Ker, M. D. (2010). 2 X VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65-nm CMOS process. In ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems (pp. 3417-3420). Article 5537864 (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems). https://doi.org/10.1109/ISCAS.2010.5537864

2 X VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65-nm CMOS process. / Lin, Chun Yu; Ker, Ming Dou.
ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2010. p. 3417-3420 5537864 (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Lin, CY & Ker, MD 2010, 2 X VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65-nm CMOS process. in ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems., 5537864, ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, pp. 3417-3420, 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010, Paris, France, 2010/05/30. https://doi.org/10.1109/ISCAS.2010.5537864

Lin CY, Ker MD. 2 X VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65-nm CMOS process. In ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2010. p. 3417-3420. 5537864. (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems). doi: 10.1109/ISCAS.2010.5537864

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title = "2 X VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65-nm CMOS process",

abstract = "With the consideration of low standby leakage in nanoscale CMOS processes, a new 2xVDD-tolerant ESD clamp circuit was presented in this paper. The new ESD clamp circuit had a high-voltage-tolerant ESD detection circuit to improve the turn-on efficiency of the silicon-controlled-rectifier-based (SCR-based) ESD device. This design had been successfully verified in a 65-nm CMOS process. The leakage current of this ESD clamp circuit under normal circuit operating condition was only ∼200 nA. Besides, this ESD clamp circuit can achieve 4.8-kV HBM ESD robustness. Therefore, this design was very suitable for mixed-voltage I/O interfaces in nanoscale CMOS processes.",

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N2 - With the consideration of low standby leakage in nanoscale CMOS processes, a new 2xVDD-tolerant ESD clamp circuit was presented in this paper. The new ESD clamp circuit had a high-voltage-tolerant ESD detection circuit to improve the turn-on efficiency of the silicon-controlled-rectifier-based (SCR-based) ESD device. This design had been successfully verified in a 65-nm CMOS process. The leakage current of this ESD clamp circuit under normal circuit operating condition was only ∼200 nA. Besides, this ESD clamp circuit can achieve 4.8-kV HBM ESD robustness. Therefore, this design was very suitable for mixed-voltage I/O interfaces in nanoscale CMOS processes.

AB - With the consideration of low standby leakage in nanoscale CMOS processes, a new 2xVDD-tolerant ESD clamp circuit was presented in this paper. The new ESD clamp circuit had a high-voltage-tolerant ESD detection circuit to improve the turn-on efficiency of the silicon-controlled-rectifier-based (SCR-based) ESD device. This design had been successfully verified in a 65-nm CMOS process. The leakage current of this ESD clamp circuit under normal circuit operating condition was only ∼200 nA. Besides, this ESD clamp circuit can achieve 4.8-kV HBM ESD robustness. Therefore, this design was very suitable for mixed-voltage I/O interfaces in nanoscale CMOS processes.

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2 X VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65-nm CMOS process

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