2 X VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65-nm CMOS process

Chun-Yu Lin, Ming Dou Ker

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

With the consideration of low standby leakage in nanoscale CMOS processes, a new 2xVDD-tolerant ESD clamp circuit was presented in this paper. The new ESD clamp circuit had a high-voltage-tolerant ESD detection circuit to improve the turn-on efficiency of the silicon-controlled-rectifier-based (SCR-based) ESD device. This design had been successfully verified in a 65-nm CMOS process. The leakage current of this ESD clamp circuit under normal circuit operating condition was only ∼200 nA. Besides, this ESD clamp circuit can achieve 4.8-kV HBM ESD robustness. Therefore, this design was very suitable for mixed-voltage I/O interfaces in nanoscale CMOS processes.

Original languageEnglish
Title of host publicationISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems
Subtitle of host publicationNano-Bio Circuit Fabrics and Systems
Pages3417-3420
Number of pages4
DOIs
Publication statusPublished - 2010 Aug 31
Event2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010 - Paris, France
Duration: 2010 May 302010 Jun 2

Publication series

NameISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems

Other

Other2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010
CountryFrance
CityParis
Period10/5/3010/6/2

Fingerprint

Clamping devices
Rails
Networks (circuits)
Electric potential
Thyristors
Leakage currents

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Lin, C-Y., & Ker, M. D. (2010). 2 X VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65-nm CMOS process. In ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems (pp. 3417-3420). [5537864] (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems). https://doi.org/10.1109/ISCAS.2010.5537864

2 X VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65-nm CMOS process. / Lin, Chun-Yu; Ker, Ming Dou.

ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2010. p. 3417-3420 5537864 (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Lin, C-Y & Ker, MD 2010, 2 X VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65-nm CMOS process. in ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems., 5537864, ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, pp. 3417-3420, 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010, Paris, France, 10/5/30. https://doi.org/10.1109/ISCAS.2010.5537864
Lin C-Y, Ker MD. 2 X VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65-nm CMOS process. In ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2010. p. 3417-3420. 5537864. (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems). https://doi.org/10.1109/ISCAS.2010.5537864
Lin, Chun-Yu ; Ker, Ming Dou. / 2 X VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65-nm CMOS process. ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2010. pp. 3417-3420 (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems).
@inproceedings{a7d556527b8948c799f508f9f10b2204,
title = "2 X VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65-nm CMOS process",
abstract = "With the consideration of low standby leakage in nanoscale CMOS processes, a new 2xVDD-tolerant ESD clamp circuit was presented in this paper. The new ESD clamp circuit had a high-voltage-tolerant ESD detection circuit to improve the turn-on efficiency of the silicon-controlled-rectifier-based (SCR-based) ESD device. This design had been successfully verified in a 65-nm CMOS process. The leakage current of this ESD clamp circuit under normal circuit operating condition was only ∼200 nA. Besides, this ESD clamp circuit can achieve 4.8-kV HBM ESD robustness. Therefore, this design was very suitable for mixed-voltage I/O interfaces in nanoscale CMOS processes.",
author = "Chun-Yu Lin and Ker, {Ming Dou}",
year = "2010",
month = "8",
day = "31",
doi = "10.1109/ISCAS.2010.5537864",
language = "English",
isbn = "9781424453085",
series = "ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems",
pages = "3417--3420",
booktitle = "ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems",

}

TY - GEN

T1 - 2 X VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65-nm CMOS process

AU - Lin, Chun-Yu

AU - Ker, Ming Dou

PY - 2010/8/31

Y1 - 2010/8/31

N2 - With the consideration of low standby leakage in nanoscale CMOS processes, a new 2xVDD-tolerant ESD clamp circuit was presented in this paper. The new ESD clamp circuit had a high-voltage-tolerant ESD detection circuit to improve the turn-on efficiency of the silicon-controlled-rectifier-based (SCR-based) ESD device. This design had been successfully verified in a 65-nm CMOS process. The leakage current of this ESD clamp circuit under normal circuit operating condition was only ∼200 nA. Besides, this ESD clamp circuit can achieve 4.8-kV HBM ESD robustness. Therefore, this design was very suitable for mixed-voltage I/O interfaces in nanoscale CMOS processes.

AB - With the consideration of low standby leakage in nanoscale CMOS processes, a new 2xVDD-tolerant ESD clamp circuit was presented in this paper. The new ESD clamp circuit had a high-voltage-tolerant ESD detection circuit to improve the turn-on efficiency of the silicon-controlled-rectifier-based (SCR-based) ESD device. This design had been successfully verified in a 65-nm CMOS process. The leakage current of this ESD clamp circuit under normal circuit operating condition was only ∼200 nA. Besides, this ESD clamp circuit can achieve 4.8-kV HBM ESD robustness. Therefore, this design was very suitable for mixed-voltage I/O interfaces in nanoscale CMOS processes.

UR - http://www.scopus.com/inward/record.url?scp=77955997292&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77955997292&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.2010.5537864

DO - 10.1109/ISCAS.2010.5537864

M3 - Conference contribution

AN - SCOPUS:77955997292

SN - 9781424453085

T3 - ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems

SP - 3417

EP - 3420

BT - ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems

ER -