In recent years, the increasing number of products for the markets of mobile communication, wearable electronics as well as the internet of things (IoT), the urgent research on the low-power operating, fast-speed and high-density memory is necessary. With continued memory technology scaling down, the volatile and non-volatile memories are facing many technological challenges such as the leakage power issue in DRAM and the endurance issue in Flash memory. The ferroelectric memory (FeRAM) is the potential candidate among emerging memories because of its fast switching speed, long endurance and low voltage operation. Recently, the FRAM technology has made significant progress due to the introduction of CMOS-compatible hafnium-oxide-based materials. Our previous studies have successfully demonstrated one-transistor (1T) ferroelectric versatile memories (VM) by strained gate engineering and ferroelectric polarization. From our research result published in 2015 IRPS, 2015 VLSI, 2016 IRPS, 2016 VLSI and 2016 SSDM (Late News), we have demonstrated a versatile ferroelectric transistor featuring a low program/erase voltages, a steep sub-60mV/dec subthreshold swing and a very low leakage current of ~1016A/μm. These performance improvements can be attributed to the ferroelectric polarization and high-speed antiferroelectric switching. To further improve the memory properties, we adopt novel strain-gate engineering to enhance ferroelectric crystallinity and strengthen the polarization effect. The memory switching characteristics of our one-transistor versatile memory (1T VM) has been verified by low program/erase voltages of <6V under a very fast pulse speed of 5~20ns. The versatile memory can be designed and switched by both DRAM- and NVM-like modes, which have the potential for the development of universal memory. In this work, we propose three technological schemes to further enable power-efficient switching for DRAM and Flash operations and also evaluate transistor for program/erase characteristics and reliability property of memory applications. The novel solutions revealed in this project includes Low-Power Ferroelectric Negative Capacitance FETs with Gate Strain, Ferroelectric Negative Capacitance FETs with Remote Plasma Defect Passivation, and Ferroelectric Negative Capacitance FETs with Highly CMOS-Compatible Dopant-Free Hafnium Oxide. The above technologies will be simultaneously integrated into the ferroelectric negative-capacitance transistors and verified through TCAD simulation and first principle calculation. Under the theoretical and experimental investigation, we successfully prove that the advantages of these low-power transistors will be applicable to apply on the future universal memory technology.
|Effective start/end date||2017/08/01 → 2019/07/31|
- Strain Engineering
- Nonvolatile Memory
- One-Transistor Memory
Explore the research topics touched on by this project. These labels are generated based on the underlying awards/grants. Together they form a unique fingerprint.