相位展開法則在可重組硬體之實現

The goal of this project is to present efficient hardware architectures for phase unwrapping operations, which are required by many imaging technologies using phase data. The existing phase unwrapping algorithms, however, have common drawback of high computational complexities. The implementation of realtime imaging systems therefore is difficult. This project aims to solve this problem by proposing hardware architectures for fast unwrapping. In the first year of this project, the hardware architecture of an FFT-based phase unwrapping algorithm is developed. The architecture has advantages of low area cost and fast computation time. In the second year, a hardware circuit for a region-referenced phase unwrapping algorithm is presented. The architecture has the advantages of low area costs. Therefore, it is well-suited for the real-time phase unwrapping of images with large sizes. To evaluate the performance of the architecture, we use field programmable gate array (FPGA) to realize the architectures. The resulting implementations are used as the hardware accelerators in a system on programmable chip (SOPC) platform for the physical performance measurement. Experimental results show that the proposed architectures are well suited for applications such as embedded digital holographic microscopy requiring high portability, low power consumption, high computational speed, and accurate phase reconstruction.