新世代高速鐵電型記憶體製程整合技術開發

The Charge Trapping Flash (CTF) non-volatile memory (NVM) provides a better scalability over Poly-Si Floating-Gate Flash device, though, the existing flash memory has an unique advantage of the low sub-pJ switching energy and vital for high-density ICs. However, as continuously scaling down the size of CTF-NVM to sub-20 nm, the fewer number of stored carriers degrade the data retention and cycling endurance significantly. Recently, the developed candidates for new nonvolatile memory (NVM) are magnetic RAM (MRAM), Resistive RAM (RRAM), and ferroelectric RAM (FeRAM). Among these emerging memories, the development of ferroelectric memory is a task of top priority owing to the several advantages, such as high speed, excellent cycling endurance, long data retention, full CMOS process compatibility and high scalability. In our early works, we have demonstrated the ferroelectric transistor with steep subthreshold swing. Recently, we successfully realize the versatile ferroelectric transistor and memory device with sub-60 mV/dec swing, publishing on the IEEE flagship conferences (2015 VLSI and 2016 VLSI). This novel ferroelectric transistor is noticeable with the properties of sub-60mv/dec subthreshold swing and ultralow off-state current (~1016A/m). Furthermore, it is compatible with FinFET process, and is of great potential for the application on 3D NAND Flash memory. Unfortunately, the device performance and reliability was degraded due to the ferroelectric gate stack defects. The issue may be a major obstacle for the future scaled device. In order to optimize the characteristic of transistors, this project proposed a comprehensive experimental design and solutions. In this project, we will propose the novel defect-passivating techniques for the specific material system in order to realize the energy-efficient and highly-reliable transistors and memory devices. Although the ferroelectric HfAlOx films own the higher thermal budget than HfZrOx films, the inevitable interface traps in HfAlOx will, as the thickness scaling down, degrade the ferroelectricity, which is accompanied with higher leakage current and other reliability issues. To prevent this issue, the fluorine plasma treatment is applied on gate stack. The results show that the defects in gate stack becomes much fewer, and that the excellent polarization switching and on/off-state switching is achieved. On the other hand, dopant-free HfO2 utilizing nitrogen defect-passivating techniques is also promoted in this project. Without the issue of dopant uniformity, dopant-free HfO2 performs well on scalability and on the potential for application on 3D structures over doped-HfO2. The techniques are helpful for the development of low power NCFET and ferroelectric memory, featuring with highly integrated and compatible ability in future nano-devices.